We designed an image memory address controller board. A pipelined addressing architecture allowed for minimum addressing cycle time. A burst mode access function allowed for efficient memory clearing. A block access function allowed for selectively clearing portions of image memory array. Interrupt generation logic for a fully Versa Module Europa (VME)-complaint interrupt structure was developed. Altera EP1810 programmable logic devices (PLDs) were used for most logic functions. The finished board had a 9U by 400 mm form factor and was fully VME-compliant.

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